Movellus
About Movellus
Movellus is the leader in Intelligent Clock Networks (ICN). Its Maestro ICN IP is deployed into a variety of applications from FPGAs and AI chips in large data centers, to power-sensitive voice NPUs devices in smart speakers and smartphones, to satellites orbiting the world providing communications. Headquartered in San Jose with R&D centers in Michigan and Toronto, the team has introduced numerous highly patented architectural innovations that significantly improve clock network performance.
Did you know that 60% of SoCs lose 30-50% performance due to clock networks?
Systems-on-chip (SoCs) have recently benefited from architectural innovations in the compute element (AI), data distribution (NOC) and memory (3D/HBM). However, the clock distribution network architectures have stayed relatively unchanged in decades. The recent explosion in complexity and size of chips combined with lack of intelligence in traditional clock distribution networks has resulted in as much as 30% SoC-level performance (or power efficiency) being left on the table for most SoCs. Surprising, unbelievable? Analyze a modern SOC focusing on the clock system and you will usually reveal a significant margin that can be used to improve system throughput (Fmax or OPS/sec), energy (OPS/Watt), and power consumption (TDP).
Workload changes causing power supply droop
Multicore chips containing arrays of compute elements in datacenter AI, automotive ADAS, smartphones, and other applications have constantly changed workloads due to diversity of applications. These changes are often in the form of a step load change and result in problematic power supply droops. Supply network latency can be the determining factor in the overall system latency and can adversely impact firmware, workload scheduling, and even the benchmarks in latency sensitive applications.
Movellus’ Intelligent clock networks help address this challenge.
Maestro, an Intelligent Clock Network IP
Maestro has been developed to address these and other issues facing SoC architects and implementation teams. Reducing and even eliminating skew, OCV and PVT effects greatly improve timing closure and reduce implementation time by as much as 55%.
Are you ready to push the limits of SoC performance? Talk to us and see how we can help. And, be sure to enter our raffle for a chance to win a GoPro Hero 9 Black.
Presenter
Meet our Team Members at the Table
Connect with Us
We will be online to talk with you live between 8:00 AM and 6:00 PM (Pacific), Monday and Tuesday, August 23rd, and 24th. If you require a different time please contact us.
-
Chat with us anytime during the conference via our conference Slack channel
-
Set up a private discussion or group meeting with your team. Just fill out our contact form and let us know your needs and interests. We’ll take it from there.
-
Don’t forget to Enter our Raffle for your chance to win a GoPro Hero 9 Black.
Products
Maestro Cloud is our most robust and feature rich intelligent clock networking platform for use in complex and high performance SoC applications including data centers and networking.
Maestro AI is an intelligent clock networking solution that can automatically compensate for on-chip variation and balance insertion delays.
Maestro Phases offers SoC architects and system developers powerful new tools that automate the design and creation of robust application-optimized clocking solutions.
Set up a private meeting by contacting us. We’ll be happy to set a time to meet with you to discuss how we can improve the PPA of your entire SoC by up to 50%.